View STV2050ATR_2296521.PDF datasheet online --- IC-ON-LINE

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september 2003 1/83 stv2050a automatic multiscan digital convergence processor n multiscan 1h, 2h, hdtv and svga applications n 6 convergence channels n 14-bit embedded dacs n 1 focus channel n second order interpolation in vertical direction n digital filtering in horizontal direction n on-chip pll n on-chip video pattern generator n automatic compensation of temperature drift and aging of external components n pattern and synchronisation signals for optional optical sensor support n adjustable horizontal and vertical size n up to 7 different data sets n self-controlled power-on sequence figure 1. functional block diagram package: pqfp80 power supply: 3.3 v tape and reel: STV2050ATR i2c control eeprom interface pattern generator focus security control ram horizontal and vertical defection corrections frame and line timebase h/v sync hr hg hb vr vg vb focus r g b
2/83 table of contents 83 1 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 pin description and pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 structure of the programming system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 overview of embedded ram organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 adjustment data sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 slave i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 ads0: ic address and pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 scls bus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.3 sdai bus data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.4 sdao bus data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 color bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 i2c i/o lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 ram allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 convergence correction values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 dynamic correction values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 common correction values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 i2c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 registers storable in the eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 registers not storable in the eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 timebases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 line locked pll and system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 horizontal timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.1 horizontal dac phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 horizontal width adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 auto-calibration of dacs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 vertical time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.1 vertical synchronization signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.2 field parity recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.3 field counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.4 convergence correction frame retrace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 master i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 6.1 read operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 write operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 security feature during data tranfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/83 table of contents 6.6 data transfer between ram and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 master clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 video pattern generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 general functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.1 pattern selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 7.1.2 pattern visibility adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 cross-hatch grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.1 horizontal grid adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.2 vertical grid adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 cursor size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.2 cursor position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 7.4 border lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.1 border lines: left / right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.2 border lines: bottom / top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 gain adjustment lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5.1 video pattern for horizontal gain cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5.2 video pattern for vertical gain cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.6 auto-alignment pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 blanking of video signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 horizontal blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 vertical blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 blanking for auto-alignment pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 fast blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 global adjustments - common parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.1 position offset (also called static) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.2 gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9.1.3 field offset canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 dynamic values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 9.3 interlace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5 interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5.1 vertical filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5.2 horizontal filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.6 normal tv operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.7 manufacturing, after-sales service, lab trial modes . . . . . . . . . . . . . . . 48 9.7.1 output of field offset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.7.2 gain and offset measuring line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.7.3 gain cursor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.7.4 field offset cursor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.8 convergence outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 dynamic focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 parabola curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2
4/83 stv2050a - 10.2 focus outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 electrical loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 loop parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 loop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 operation of the electrical loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5 output/input pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5.1pora, porb and porc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5.2ogah and ogav pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12 optical loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.1 principal of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2 optt sensor port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.1optt pin used as an input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.2optt pin used as an output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3 opti sensor status port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13 current reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14 securities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.2 hamming encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.3 security output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 15 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16 ic status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17 bus expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19 recommanded operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.2 current reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.3 video pattern outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.3.1dacs for rgb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 20.3.2fblk output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4 focus dacs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4.1focus reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.4.2focus signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.5 convergence dacs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.6 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.7 master i2c time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.8 horizontal and vertical synchronization inputs . . . . . . . . . . . . . . . . . . . . 67 20.9 tbu outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 20.10electrical loop pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 22 electrical pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23 i2c bus register variable glossary and register location . . . . . . . . . . . . . 72
5/83 stv2050a - 24 index of i2c bus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2
6/83 stv2050a - general overview 1 general overview 1.1 system block diagram figure 2. tv set convergence system diagram to/from microprocessor h/v deflection power stage convergence application circuit r g b hv tuner if video sound focus amplifier 6x 1x h v bl r g b r g b r g b focus gnd gnd r g b r g b gnd gnd hv hv i 2c bus eeprom(s)
7/83 stv2050a - general overview 1.2 device block diagram figure 3. stv2050a block diagram dagv dngv vccb dabv dnbv gndb ogav ogah gndp refc refn vccp darh dnrh vcca dagh dngh gnda dabh dnbh vccg gndg vcch gndh flt2 vccf synh synv gndj gndl vccj vccl tbu7 tbu6 tbu5 tbu4 tbu3 tbu2 tbu1 tbu0 sdam sclm gndq gndk vccq vcck sdao sdai scls vblk test vccn rest eclk gndn vidr vidg vidb vccd gndd oscl gres gndf filt pora porb porc pout gndm mlin optt vccm opti ads0 gndc focr focs vccc darv dnrv i 2c slave vertical filters horizontal filters d a d a d a d a d a d a d a d a d a 4 4 4 14 14 14 14 14 14 video pattern generator d a d a 6 6 011111h interpolation gain/offset bandgap loop red memory green memory blue memory focus memory control i2c master i2c oscillator 400 khz pll pll logic system clock vertical filter reset vsync system bus expander port interface timebase memory register bus iref logic parallel i 2c bus digital power supplies start logic dac enable grid timing dac timing calibration analog power supplies dac focus processor
8/83 stv2050a - general overview 1.3 application circuit an application circuit with 2nd eeprom, electrical offset and gain adjustment loop and op- tical sensors is shown in the following figure. figure 4. application circuit 11 test 14 eclk r b g to video 16 vidr 17 vidg 18 vidb 10 vblk vcca 50 3.3 v analog r b g pora 80 porb 79 porc 78 r g b ogav 58 ogah 57 h v 13 rest +15 v -15 v 27 synh 28 synv deflection h v 3.3 v 26 vccf 20 gndd 3.3 v 3.3 v analog 71 ads0 8 sdai i2c bus to p 9 scls 22 gres 2 sclm 1 sdam 3.3 v 3.3 v 25 flt2 7 sdao data clk 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v analog 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v focus f 43 gndg 41 gndh 29 gndj 4 gndk 30 gndl 76 gndm 15 gndn 3 gndq 42 vcch 31 vccj 6 vcck 32 vccl 73 vccm 12 vccn 5 vccq 24 filt filter 3.3 v 3.3 v -3.3 v 3.3 v ext. + int. reset 3.3 v 44 vccg darh 52 dnrh 51 dagh 49 dngh 48 dabh 46 dnbh 45 gnda 47 3.3 v analog vccb 62 darv 66 dnrv 65 dagv 64 dngv 63 dabv 61 dnbv 60 gndb 59 gndi 53 refn 54 refc 55 gndp 56 pout 77 vccc 70 dacf 69 fref 68 gndc 67 opti 72 optt 74 mlin 75 filter 21 oscl 3.3 v 8 7 6 5 1 2 3 4 a 010 8 7 6 5 1 2 3 4 m24164 a 011 +3.3 v h v +3.3 v h v +3.3 v h v +3.3 v -3.3 v horizontal vertical tbu0 40 tbu7 33 8 ports 23 gndf 19 vccd 3.3 v digital m24164
9/83 stv2050a - general overview 1.4 pin description and pinout diagram the following legend applies to the pin description table below: x = undefined hz = high impedance "0" = low level output "1" = high level output table 1. pin description pin no. pin name reset status and remarks description 1 sdam hz master bus: "data" 2 sclm master bus: "clock" 3 gndq digital supply: ground 4 gndk digital supply: ground 5 vccq core / ram digital supply: 3.3 v 6 vcck core / digital supply: 3.3 v 7 sdao "0" slave bus: "data" output 8 sdai slave bus: "data" input 9 scls slave bus: "clock" 10 vblk video pattern blanking 11 test must be grounded reserved 12 vccn shield supply digital supply: 3.3 v 13 rest "0" reset 14 eclk must be grounded reserved 15 gndn digital supply: "ground" 16 vidr 0 volts video pattern output: "red" 17 vidg 0 volts video pattern output: "green" 18 vidb 0 volts video pattern output: "blue" 19 vccd video generator supply: 3.3 v 20 gndd video generator supply: ground 21 oscl hz rc for internal oscillator 22 gres hz r for internal oscillator 23 gndf pll supply: ground 24 filt hz filter for pll 25 flt2 hz filter for pll 26 vccf supply pll: 3.3 v 27 synh horizontal synchronization input 28 synv vertical synchronization input 29 gndj digital supply: ground 30 gndl digital supply: ground 31 vccj core digital supply: 3.3 v 32 vccl ring / buffer digital supply: 3.3 v 33 tbu7 x i2c bus expander 34 tbu6 x i2c bus expander 35 tbu5 x i2c bus expander 36 tbu4 x i2c bus expander
10/83 stv2050a - general overview 37 tbu3 x i2c bus expander 38 tbu2 x i2c bus expander 39 tbu1 x i2c bus expander 40 tbu0 x i2c bus expander 41 gndh analog supply: ground 42 vcch d/a interface analog supply: 3.3 v 43 gndg analog supply: ground 44 vccg analog supply: 3.3 v 45 dnbh hz horiz. convergence output: blue, negative 46 dabh hz horiz. convergence output: blue, positive 47 gnda horiz. convergence output supply: ground 48 dngh hz horiz. convergence output: green, negative 49 dagh hz horiz. convergence output: green, positive 50 vcca hz horiz. convergence output supply: 3.3 v 51 dnrh hz horiz. convergence output: red, negative 52 darh hz horiz. convergence output: red, positive 53 gndi floating gnd for bandgap filter 54 refn reference current code 0(hex) i ref loop for h&v convergence & focus 55 refc x filter pin for i ref current 56 gndp i ref gnd for bandgap 57 ogah hz horiz. reference output for electrical loop 58 ogav hz vert. reference output for electrical loop 59 gndb hz vert. convergence output supply: ground 60 dnbv hz vert. convergence output: blue, negative 61 dabv hz vert. convergence output: blue, positive 62 vccb vert. convergence output supply: 3.3 v 63 dngv hz vert. convergence output: green, negative 64 dagv hz vert. convergence output: green, positive 65 dnrv hz vert. convergence output: red, negative 66 darv hz vert. convergence output: red, positive 67 gndc focus supply: ground 68 focr focus reference output 69 focs focus signal output 70 vccc focus supply 71 ads0 i2c slave bus address selection 72 opti input for optical sensor support 73 vccm ring / inputs digital supply: 3.3 v 74 optt input i pin: latched at measuring line or with sys. clock; o pin: push/pull, output can be switched to high impedance 75 mlin "0" measuring line signal output 76 gndm digital supply: ground pin no. pin name reset status and remarks description
11/83 stv2050a - general overview figure 5. pinout diagram 77 pout hz protection pin control 78 porc input normally used for electrical loop feedback detec- tion. can also be set as an inpout or an output. 79 porb 80 pora pin no. pin name reset status and remarks description dagv dngv vccb dabv dnbv gndb ogav ogah gndp refc refn gndi darh dnrh vcca dagh dngh gnda dabh dnbh vccg gndg vcch gndh flt2 vccf synh synv gndj gndl vccj vccl tbu7 tbu6 tbu5 tbu4 tbu3 tbu2 tbu1 tbu0 sdam sclm gndq gndk vccq vcck sdao sdai scls vblk test vccn rest eclk gndn vidr vidg vidb vccd gndd oscl gres gndf filt 1 24 pora porb porc pout gndm mlin optt vccm opti ads0 gndc focr focs vccc darv dnrv 80 25 40 41 64 65 5 10 15 20 30 35 45 50 55 60 70 75 pqfp80
12/83 stv2050a - structure of the programming system 2 structure of the programming system 2.1 data storage the stv2050a is a programmable device. some of the data, mainly the convergence param- eters, must be able to be easily changed during tv set alignment or by the user, and must be memorized when the tv set is switched off in order to be recovered when switched back on. this data must therefore be stored in eeprom. the stv2050a has an embedded ram for storing data used in real time at a high speed. in order to simplify the microcontroller software, and to ensure a quick startup, the stv2050a directly controls one or more (or up to seven) eeproms. the stv2050a has 2 ports for i2c connections: C the first one is used only for slave connections: it is used to interface with a microcon- troller in order to control the ic (customer adjustments,...). the microcontroller can write and read the embedded ram via this slave port. C the second one is used only for master connections: it is used to interface the stv2050a with the eeprom that stores the convergence data and some user adjustments. the transfer of data between the eeprom and the embedded ram is fully managed by the stv2050a. figure 6. i2c bus data transfer data tranfer control stv2050a from / to mcu slave i2c interface logic core embedded ram master i2c interface eeprom 2k x 8 bits
13/83 stv2050a - structure of the programming system 2.2 overview of embedded ram organization the ram consists of 3 banks: the first one, the red and i2c bank, uses 24-bit words. the two other banks, the green bank and blue bank, both use 22-bit words. each bank has 208 words with addresses from 00(hex) to cf(hex). these 3 x 208 words are allocated to the dynamic convergence parameters. (refer to sec- tion 4.1 "convergence correction values" on page 18 .) the red and i2c bank has 33 additional words: addresses from d0(hex) to ef(hex) and fe(hex). these words are used to buffer the i2c bus registers. as shown in this figure, each word can be pointed to by a sub-address (sa). thus, each sub- address points to 24- (or 22-, depending on the bank) bit wide words. a word virtually consists of three bytes (24-bits) named d0, d1 and d2 as shown in the following figure. the bit order is named as follows: d0[7] is the msb and d2[0] is the lsb note : bit d0[7:6] is not physically implemented in the green and blue banks. msb lsb d0 byte d1 byte d2 byte bit 765432107654321076543210
14/83 stv2050a - structure of the programming system figure 7. color banks note: bits 22 and 23 of the red and i2c bank may be used for general purposes. they are stored to- gether with the convergence data in the external eeprom. 2.3 adjustment data sets the set of data stored at addresses d0 to e2 is called an ads (adjustment data set). the stv2050a can store up to three adss in one standard eeprom. refer to section 6 " master i2c bus interface" on page 28 . 24 bits 22 bits 22 bits red and i2c green green blue 00 cf d0 e2 dynamic correction values for the green channel dynamic correction values for the blue channel dynamic correction values for the red channel protected i2c registers non-protected i2c registers e3 ef fe bank: i2c sub-address (sa) ajustment data set
15/83 stv2050a - slave i2c bus interface 3 slave i2c bus interface 3.1 features the i2c interface is controlled by 4 pins: 3.1.1 ads0: ic address and pll mode the level at this pin corresponds to bit 1 in the first byte in bus transmissions. C if ads0 is connected to gnd, the analog outputs will be automatically switched on after the reset sequence, and once the internal pll is activated. C if the pin is connected to vcc, the dacs will remain in high impedance. the internal pll is inhibited, and the ic must use an external pll. 3.1.2 scls bus clock the polarity and timing for this pin comply with i2c bus specifications. 3.1.3 sdai bus data input the polarity and timing for this pin comply with i2c bus specifications. 3.1.4 sdao bus data output the polarity reversal and timing for this pin comply with i2c bus specifications. abbreviations used: s = start condition p = stop condition da = device address dr = device address for read dw = device address for write sa = sub-address d0, d1,... dn = data bytes the slave accepts the following da subaddresses depending on the hardware configuration defined on pin ads0. for the 00 to cf address range (ram), an autoincrement function can be enabled using the aie (auto increment enable) bit in the e7 register. ads0 0 (grounded, internal pll only) dr = 39, dw = 38 1 (3.3 volt, external pll only) dr = 3b, dw = 3a aie 0 = autoincrement disabled 1 = autoincrement enabled
16/83 stv2050a - slave i2c bus interface if the autoincrement function is enabled, the internal address is automatically incremented after 3 bytes are either written or read. when the autoincrement counter reaches the cf ad- dress, the counter stops counting and any additional data will be written to or read from the cf address. 3.2 color bank selection as previously mentioned, the embedded ram is mapped in 3 banks called the red and i2c bank, green bank and the blue bank. a bank is selected using the cbs[1:0] (color bank selection) bits located in the e7 register address. however, sub-addresses d0 to ef and fe (physically mapped in the red and i2c bank) are independent of the actual bank selection. 3.3 write commands three formats of write commands are supported: C 5-byte write commands to any valid sub-address s dw sa d0 d1 d2 p if the auto-increment function is enabled, the internal address is at sa+1 after the command, otherwise it is still at sa. C 2-byte write commands for defining a sub-address cursor position or for changing the current sub-address without transmitting data. s dw sa p the sub-address is at sa after the command. C auto-increment write commands for sub-address range 00 to cf if the auto-increment function is enabled, the internal address counter is incremented each time 3 bytes are written: s dw sa i d i 0 d i 1 d i 2 d i+1 0 d i+1 1 d i+1 2... dn p otherwise every group of 3 bytes is written to sa and the sub-address does not change. s dw sa i d i 0 d i 1 d i 2 d i 0 d i 1 d i 2... ... dn p when a group of three data bytes within the 00 to e2 address range has been received, the slave will store them in the appropriate embedded ram location. only complete groups of three data bytes are stored. i2c registers start to be updated when the first data byte is re- ceived. only complete bytes are written. all write commands which do not comply with the formats described above are rejected. cbs[1:0] 00 = red and i2c bank selected 01 = green bank selected 10 = blue bank selected 11 = red and i2c bank selected
17/83 stv2050a - slave i2c bus interface 3.4 read commands read commands may access the ic internal ram as well as all i2c registers. read com- mands in the 00 to cf range read from the ram bank that is defined by the two cbs bits that have been previously transmitted to the e7 register by a write command. addresses in the d0 to e2 range are mapped to the corresponding section of the red color ram if the rrp bit in the ef register is 0. otherwise the corresponding internal register values are transmitted. if the sa is in the 00 to cf address range, the position of the cursor is implicitly defined by the sa. an access to any other sas will switch off the cursor. it will be switched on again if an ad- dress in the 00 to cf range is selected. three formats of read commands are supported: C random read commands from any valid ic internal address s dw sa s dr sa d0 d1 d2 p if the auto-increment function is enabled, the internal address is at the sa+1 after the com- mand, otherwise it is still at the sa. C read commands from the actual internal address s dr sa d0 d1 d2 p if the auto-increment function is enabled, the internal address is at the sa+1 after the com- mand, otherwise it is still at the sa. C auto-increment read commands from addresses within the 00 to cf address range with random start address. s dw sa s dr sa d0 d1 d2...... dn p if the auto-increment function is enabled, the internal address counter is incremented after 3 bytes are read, otherwise the sa is always read and the internal address does not change. when the last byte of the cf address has been transmitted, the ic internal auto-increment ad- dress counter stops counting and the cf value will be read out again. 3.5 i2c i/o lines digital filters suppress pulses that are less than 1 or 2 clock pulses at the sdai and scls in- puts.
18/83 stv2050a - ram allocation 4 ram allocation 4.1 convergence correction values the convergence correction values are either dedicated to each correction point of each red/ blue/green channel, or common for all points of each channel. (refer to section 9 "conver- gence" on page 45 .) the values are grouped into 2 families: C dynamic correction values C common correction values 4.1.1 dynamic correction values the dynamic values are stored as described in section 2.2 "overview of embedded ram organization" on page 13 . for each red, green and blue channel, the following can be stored in the embedded ram: C 13 horizontal "dynamic" correction values on 10 bits, plus 1 parity bit C up to 16 vertical "dynamic" correction values on 10 bits, plus 1 parity bit for each correction point there is one corresponding word in the 00(hex) to cf(hex) sub-ad- dress range. bits are stored in the corresponding red bank, green bank and blue bank as follows: C bit d1[3] is the horizontal correction parity bit C bit d1[2] is the vertical correction parity bit C bits d1[3:2] are generated by the stv2050a. their value can be read out only. note : the stv2050a automatically checks the parity bits of each convergence value before applying them to the dacs. refer to section 14 "securities" on page 62 . the sub-address corresponds to the coordinates of the point on the screen where the vertical and horizontal lines meet, as shown in the following figure: msb lsb byte d0 byte d1 byte d2 bit 765432107654321076543210 horizontal correction[9:0] vertical correction[9:0]
19/83 stv2050a - ram allocation figure 8. addressing a correction point 4.1.2 common correction values the common correction values are stored in the adjustment data sets of the red and i2c channel. see figure 7 "color banks" on page 14 and section 9.1 "global adjustments - common parameters" on page 45 . 4.2 i2c registers all i2c registers are implemented in the red and i2c bank of the embedded ram. as it can be useful to store some of the i2c register content in the eeprom, the embedded ram allo- cation is divided into two parts: C from sub-address d0 to e2 (included), contents can be stored in the eeprom, and can then be restored, C from sub-addresses e3 to ef and fe, contents are lost when the stv2050a is switched off. visible screen area 0 1 15 0 1 2 12 2 6 7 address: 76(hex)
20/83 stv2050a - ram allocation 4.2.1 registers storable in the eeprom msb lsb byte d0 byte d1 byte d2 sa 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 d0 rfh[7:0] gfh[7:0] bfh[7:0] d1 rfv[7:0] gfv[7:0] bfv[7:0] d2 orh[7:0] ogh[7:0] obh[7:0] d3 orv[7:0] ogv[7:0] obv[7:0] d4 x pd c pd b pd a x po c po b po a x pl t go s hv m gav [1:0] gah [1:0] x x x x x x x x d5 pr s 0 am s[0 bga[4:0] pm h pm v x x x x ml e mln[8:0] d6 pbh[3:0] pbv[3:0] hb e ha e hvb[5:0] vb e va e vvb[5:0] d7 x hgp[6:0] tv h tv v bph[5:0] fa s st a bpv[5:0] d8 ac w x hgd[5:0] acl[1:0 ] hrd[5:0] afs[1:0 ] asp[2:0] fs o hif[1:0] d9 vgp[7:0] vg p vf p vgd[5:0] vfp[7:0] da iie ifa x icv[5:0] vst[7:0] fsb[7:0] db dc t[8] hdp[6:0] dct[7:0] dcb[7:0] dc crh[7:0] cgh[7:0] cbh[7:0] dd crv[7:0] cgv[7:0] cbv[7:0] de fv1[5:0] fv2[5:0] fv3[5:0] fvr[5:0] df ol e gl e fin di o di g x x x nom[7:0] tol[7:0] e0 rch[3:0] rcv[3:0] gch[3:0] gcv[3:0] bch[3:0] bcv[3:0] e1 srh[7:0] sgh[7:0] sbh[7:0] e2 srv[7:0] sgv[7:0] sbv[7:0]
21/83 stv2050a - ram allocation 4.2.2 registers not storable in the eeprom note : x = dont care, 0 or 1: the corresponding bit must be set to this value for normal operation. msb lsb byte d0 byte d1 byte d2 add 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 e3 st l x x gc d dh v pp l cd o cd n stv2050a code = 30(hex) s0 1 s1 9 reserved s0 2 s0 3 e4 x pd c pd b pd a x po c po b po a x pl t go s hv m gav [1:0] gah [1:0] s0 1 s1 9 ms y el o x pic pib pia e5 op i od s oo s od t x x x x s09 [3:0] s10 [3:0] s0 1 s1 9 s0 5 s1 1 s12 [3:0] e6 x x x x x x x x s13[7:0] s14[7:0] e7 aie x x x x x cbs [1:0] x x x x x x x x x x x x x x x te 1 e8 mvr[7:0] mvg[7:0] mvb[7:0] e9 eepro- madd [2:0] x x x ads[1:0 ] rwm [2:0] x ham[3:0] s0 1 s1 9 x x stx[3:0] ea x x x x vd c cov[2:0] gc p vh v x pas[4:0] x x x x x x x x eb x x ho1 [5:0] hg1[3:0] x x ho2[5:0] hg2[3:0] ec x x vo1[5:0] vg1[3:0] x x vo2[5:0] vg2[3:0] ed x x ho3[5:0] hg3[3:0] x x ho4[5:0] hg4[3:0] ee x x vo3[5:0] vg3[3:0] x x vo4[5:0] vg4[3:0] ef xxxxx ru e ru 1 ru 2 xxxx te 2 te 3 te 4 rr p xxxxxx00 fe x ss e dt e 0000000000000 tbu[7:0]
22/83 stv2050a - timebases 5 timebases 5.1 line locked pll and system clock a frequency-multiplying pll derives the internal system clock from the incoming signal at the synh pin. this signal is derived from horizontal deflection. figure 9. line-locked pll and system clock the pll is designed to drive 1h, 2h, hdtv and svga applications. two loop filters can be implemented using the filt (pin 24) and flt2 (pin 25) pads. the selection can be forced by the prs bit in the d5 register. the horizontal deflection is often turned off when switching tv set modes. therefore the pll provides a base frequency when the external sync signal is missing (both h and v sync sig- nals are missing). prs 0 = filt selected (2h and above range operation recommended) 1 = flt2 selected (1h range operation recommended) pll 15 k 10 nf 15 k 10 nf 100 nf 1.5 nf synh prs stv2050a system clock
23/83 stv2050a - timebases the n (clk/line) ratio between the system clock and the incoming sync signal is calculated using the hgd[5:0] and hrd[5:0] values in the d8 register. (refer to section 7.2.1 "horizontal grid adjustment" on page 35 ): n (clk/line) = 14 * (hgd+1) + 2 * (hrd+1) where: n (clk/line) < 512 hgd > 15 hrd > 15 for all modes, in normal operation, the incoming timing signal at the synh pin will not have a phase deviation greater than 2 s from line to line. greater phase deviations may occur when switching modes or changing channels. the pll is expected to recover from these events and lock within one vertical field of consistent phase that is within the normal horizontal operation limits. 5.2 synchronization inputs the two synchronization inputs, synh (pin 27) and synv (pin 28) slice the line or the frame flyback, respectively, via a schmitt trigger. this also ensures a very stable detection of the synchronization signals, regardless of the temperature. figure 10. synchronisation signals 5.3 horizontal timebase the horizontal timing is based on the built-in pll. 5.3.1 horizontal dac phase in order to compensate the delay of the external amplifiers and the response time of the con- vergence coils (t d ), the values for convergence correction are given out prior to the corre- sponding horizontal video position. the time delay between video position and the output of v up v cc v in 0 1 logi c level (1) (2) v down v d
24/83 stv2050a - timebases the corresponding convergence correction value is defined by the horizontal dac phase hdp[6:0] value in the db register. the following range for the horizontal dac phase is allowed: 0 hdp 2 hgd the timing of the dac output leads the most if hdp is equal to zero. figure 11. horizontal dac phase 5.3.2 horizontal width adjustment in order to fit the video pattern into the full visible area of the screen, the width of the pattern may be adjusted. horizontal width adjustment is done by changing the number of clock cycles between the vertical grid lines during retrace and the visible grid. the timing for the corre- sponding dac values is changed accordingly. refer to section 7.2.1 "horizontal grid adjust- ment" on page 35 . 5.3.3 auto-calibration of dacs all the dacs of the stv2050a can be automatically calibrated. this feature ensures a high matching stability in both time and temperature. the process involves the sequential calibra- tion of 120 cells. to ensure optimal results, each cell must be calibrated at least every 4 ms. the duration of one cell calibration must be greater than 2us. this duration is controlled by the internal calibration clock. the calibration clock is generated using a divider of the system clock. (refer to section 5.1 "line locked pll and system clock" on page 22 ). the di- vision ratio is programmable via the acl[1:0] bits in d8. hgn n n-1 n-2 n-3 n+1 n+2 n+3 hgrid hgd hgd hdp n n-1 n-2 n+1 n+2 n+3 n+4 dac output coil current
25/83 stv2050a - timebases autocalibration can take place either during the full line, or during the line retrace only. this is controlled by the acw bit in the d8 register. if the during line retrace only autocalibration is selected, the number of dac cells cali- brated during each line retrace is defined by the afs[1:0] value in the d8 register. two autocalibration modes can be selected by the ams[0] bit in the d5 register. the time interval for auto-calibration is normally centred to the retrace. but it is possible to ad- just the start point by programming the asp[2:0] bits in the d8 register. one step corresponds to one system clock cycle. 5.4 vertical time base 5.4.1 vertical synchronization signal the vertical timing is based on the vertical deflection signal. a debounce filter is implemented to prevent interference on the synv signal caused by crosstalk, mainly from horizontal deflec- tion. this filter accepts a rising edge of the synv signal only when synv is 'low' for a time 3 8 tv lines (determined by 8 pulses at the synh input). figure 12. vertical synchronization signal acl[1:0] 00: no calibration 01: division by 16 10: division by 32 11: division by 48 acw 0: during line retrace only 1: during the full line afs[1:0] 00: 1 cell / line 01: 2 cells / line 10: 3 cells / line 11: 4 cells / line ams[0] 0: the autocalibration process is not synchronized to vertical timing 1: the autocalibration is synchronized to vertical ic timing. the counter which selects the dac cells that are to be calibrated is reset on each frame retrace. > 8h v - deflection synv vsync
26/83 stv2050a - timebases 5.4.2 field parity recognition in the case of a standard stv2050a implementation, synchronization is achieved using sig- nals extracted horizontally (line flyback) and vertically (frame flyback). unfortunately, de- pending on the components and the configuration, the phase relationship between these sig- nals is not the same in every tv chassis. in this case, field parity recognition can be unreliable unless special features are implemented. the stv2050a can achieve perfect field parity rec- ognition using the vertical sync shift (vst). when the vst[7:0] bits in the da register are set to the optimum value, the stv2050a distin- guishes perfectly between the two fields. this is used to control the interpolation of the con- vergence values and the video pattern generator according to the interlaced scanning scheme. the correct vst value can be evaluated by measuring the timing of the vertical pulse. this timing is measured by the stv2050a, and the results are stored in the s13[7:0] and s14[7:0] bits in the e6 register. in non-interlaced mode, field recognition can be switched off by the iie bit in the da register. 5.4.3 field counter a 4-bit field counter is implemented for controlling the optical alignment procedure. the counter value is stored in the s12[3:0] bits in the e5 register (read only). this counter will be reset to 0000 at ic power-up and will be incremented after every vertical reset. the counter will overflow from 1111 to 0000. (the counter will not be reset when the e5 register is read.) 5.4.4 convergence correction frame retrace this is the time interval defined as follows: C start at grid line number 11 + dcb[7:0] bits in the db register, C stop at 2 tv lines after the frame pulse + dct[8:0] bits in the db register; where dcb and dct are the number of tv lines. iie 0 = interlace off 1 = interlace on
27/83 stv2050a - timebases figure 13. vertical time base vertical pulse vertical convergence frame retrace dcb lines dct lines horizontal pulses 1 tv line vertical grid number 11 register update mln lines measurement line
28/83 stv2050a - master i2c bus interface 6 master i2c bus interface a master i2c bus implemented in the stv2050a is used to transfer data between the ic em- bedded ram and the external 2k x 8-bit eeproms (for example, the 24164 manufactured by st). the protocol supports up to 7 eeprom addresses which can be selected using the 3 eepromadd [2:0] bits in the e9 register. master activities are initiated either by an external reset of the stv2050a, or by commands from an external mcu via the slave i2c bus. the following features are implemented in the master i2c bus interface: C reset the i2c bus to the eeprom C read a specified data range from eeprom to ram C write a specified data range from ram to eeprom C check if an eeprom register is available C power-on sequence C security features C generate status information the organization of data in the embedded ram is completely different from that in the eeprom register. therefore, address transformations are required in both directions. this is carried out by the stv2050a in a way that is fully transparent for the user. the external mcu initiates a master access to the eeprom by writing a command to the e9 address. this command contains information about the type of access and specifies one of seven eeproms (refer to section 6.6 "data transfer between ram and eeprom" on page 30 ). the embedded ram contains convergence correction data and one adjustment data set (ads) to control the various modes of the stv2050a. three adss can be stored in the eeprom. one of these three sets is selected by the two ads[1:0] bits in the e9 command to be mapped to the register ram area inside the ic. any command sent from the mcu to the e9 address while the master is active will be lost. also, the eeprom address which is included in this command will not be accepted. before addressing the e9 register, the mcu should check if the master is active. to do this, the rwm[2:0] bits in the e9 register must be set to 001 (bin). the corresponding status is given on the stx[2] bit. if any error are detected during the transmission of data on the eeprom i2c bus, the trans- mission is stopped and the corresponding stx[3] bit of the status section of the e9 register is set. read or write modes can be selected by setting bit rwm[2] in the e9 register. rwm[2] 0 = read mode 1 = write mode
29/83 stv2050a - master i2c bus interface 6.1 read operation modes two modes of read sequences are implemented by selecting the rwm[1:0] bits. 6.2 write operation modes three modes of write sequences are implemented by selecting the rwm[1:0] bits. 6.3 power-on sequence at power-on, the master interface runs a special sequence to build up the convergence cor- rection data and the stv2050a ram is loaded with data from a user-specified eeprom. 6.4 security feature during data tranfers since access to an eeprom register is critical with respect to system performance, all eeprom access commands in the e9 register, together with the corresponding addresses, are protected by the 2-bit, error-detecting hamming code. if the circuit detects an error, the master will not initiate an eeprom access and an error bit will be set in the status register. if any errors are detected during the transmission of data on the i2c bus, the transmission is stopped and the corresponding stx[3] bit in the status section of the e9 register is set. 6.5 status information four stx[3:0] bits are available in the status section of the e9 register. these bits continu- ously reflect the activity and the error status of the master i2c bus interface. C stx[3] = transmission error this bit is set to low if an error in the transmission of an eeprom access command was detected. it remains low until the next error-free transmission to register e9 is completed. C stx[2] = eeprom access finished this bit is set to low when the master i2c-bus interface has completed bus activities. this bit does not display the completion of an eeprom access. this bit is set high by the master at the start of a new bus sequence or by the slave after reading status register e9. C stx[1] = eeprom r/w this bit is set to low when the master has initiated an access to the eeprom. it remains low until the sequence is finished or the sequence is terminated by an access error. rwm[1:0] 11 (bin): read all convergence data and an ads 10 (bin): read an ads only rwm[1:0] 01 (bin): write all convergence data and one of the three adss 00 (bin): write only one of the adss 10 (bin): write only the static (position offset) values
30/83 stv2050a - master i2c bus interface C stx[0] =eeprom problem if a read or write sequence has been terminated with an access error, the stx[0] bit is set to low. it is set back to high when the master starts the next r/w sequence. 6.6 data transfer between ram and eeprom data is transfered using the following i2c bus sequence after a bit in the e9 register has been read or written: s dw sa d0 d1 d2 p where: C sa = e9: selection of the e9 register, eepromadd[2:0] is the hardware eeprom address used by the i2c master, C rwm[2:0] selects the read or write mode as previously described, C ham[2:0]: hamming code used to protect the d0[7:0] and d1[7:4] data bits. refer to section 14.2 "hamming encoding" on page 62 . the total transfer lasts approximately 200 ms if the i2c master clock is operating at 70 khz. msb lsb byte d0 byte d1 byte d2 add 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 e9 eepro- madd [2:0] xxx ads[ 1:0] rwm [2:0] x ham[3:0] x x x x stx[3:0]
31/83 stv2050a - master i2c bus interface 6.7 master clock frequency the i2c master uses its own timebase with a local oscillator. the frequency is fixed by external filter (r1/c and r2) as shown in figure 14 "master i2c clock" on page 31 . typical values are: C r1 = 82 k w C r2 = 10 k w C c = 33 pf figure 14. master i2c clock i2c master time base r1 c r2 stv2050a scl out
32/83 stv2050a - video pattern generator 7 video pattern generator the stv2050a provides a built-in video pattern generator for convergence adjustments. the rgb signals are generated by 4-bit dacs with a voltage output. the fblk signal is used to switch the rgb source inside the tv set. the fblk is a fixed-voltage output. the video pat- tern generator delivers five types of video patterns: C cross-hatch grid : displays the physical locations corresponding to the stored correction values. refer to sec- tion 7.2 "cross-hatch grid" on page 35 . C cursor : a crosshair is displayed at the place corresponding to the current addressed memory loca- tion. C border lines : used to adjust the convergence at the horizontal and vertical edges of the visible screen ar- ea. refer to section 7.4 "border lines" on page 37 . C gain adjustment lines : used to easily adjust the gain of the convergence channels and to optimize interlace mode. C auto-alignment pattern : supports an auto-alignment procedure. the video generator also produces the control signals for the optional optical loop functions. the patterns can be modified using several parameters in the registers of the stv2050a.
33/83 stv2050a - video pattern generator figure 15. auto-alignment pattern note : it is not possible to display both cursors simultaneously as shown. 7.1 general functions 7.1.1 pattern selection the color components (rgb) for the video pattern can be separately switched on and off by the cov[2:0] bits in the ea register. if the control bit for one color is set to 0, the corresponding dac output is switched to 0v. the type of the pattern is selected by the pas[4:0] bits in the ea register. cov[2] 0: red = off 1: red = on cov[1] 0: green = off 1: green = on cov[0] 0: blue = off 1: blue = on pas[4] 0: auto-alignment pattern off 1: auto-alignment pattern on pas[3] 0: small cursor 1: large cursor pas[2] 0: cursor off 1: cursor on small cursor large cursor visible screen border lines 0 1 15 0 1 2 12 2 progammable for h zoom effect first two grids only programmable distance auto-alignment pattern
34/83 stv2050a - video pattern generator the fblk output is switched to high voltage when at least one color is activated by the cov bits in the ea register when the sta bit in the d7 register is activated. if no color is selected, the fblk output is switched to low voltage. for other features of the fblk pin, refer to sec- tion 8.4 "fast blanking" on page 43 . the video signal representing a vertical line (grid, border, cursor) has the shape of a pulse with a width of one system clock cycle. 7.1.2 pattern visibility adjustment since the bandwidth of the rgb signal path is limited, horizontal and vertical lines may appear on the screen with different brightness levels. to compensate for this effect, it is possible to adjust the brightness values for the horizontal line (pbh[3:0]) bits and the vertical line (pbv[3:0]) bits in the d6 register of the video pattern. the video brightness has 4-bit resolution. the 0(hex) value corresponds to the 0.0 v output from the video dacs. the 1(hex) value corresponds to a typical 0.6 v output. all other steps are equidistant. figure 16. pattern visibility adjustment if the pbh bit is set to zero, the amplitude of the auto-alignment pattern is determined by the pbv bit. using the vdc bit in the ea register, the frequency compensation of the video dacs can be adapted according to the system clock. pas[1] 0: grid off 1: grid on pas[0] 0: border off 1: border on vdc 0: low current 1: high current 0.6 v 2.3 v 0000 0001 0010 1111 analog output digital value
35/83 stv2050a - video pattern generator 7.2 cross-hatch grid the convergence values are adjusted and stored for an array of 16 x 13 points. these points can be displayed by the grid lines of the video generator. the deflection correction at the grid points corresponds to the digitally stored values. several programming features are used to adapt the grid, and therefore the convergence adjustment, to the needs of the application. all parameters for the grid are included in the data set stored in the internal ram. 7.2.1 horizontal grid adjustment the horizontal distance of the grid lines is determined by the values of the hgd[5:0] and hrd[5:0] bits in the d8 register. refer to figure 17 "horizontal grid adjustment" on page 35 . between each grid line, a minimum of 16 system clock cycles is required for calculating the convergence. (refer to section 5.1 "line locked pll and system clock" on page 22 ). the geometrical distance between two vertical grid lines can be modified by adding clock cy- cles between the visible grid lines (hgd) or by adding clock cycles during the horizontal re- trace (hrd). C hgd: horizontal grid distance during active line. C hrd: horizontal grid distance during line retrace. the left-right position is controlled by the hgp[6:0] bits in the d7 register. figure 17. horizontal grid adjustment 7.2.2 vertical grid adjustment in the same way, the vertical grid adjustment is done using the vgp[8:0] and vgd[5:0] bits in the d9 register. 0 1 2 3 4 5 6 7 8 910 12 13 14 15 11 0 1 2 15 retrace retrace h-flyback hsync grid (hgp=0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 15 0 retrace retrace grid (hgp>0) hgp
36/83 stv2050a - video pattern generator figure 18. vertical grid adjustment if the vgp bit is programmed to 0, the grid starts with the first line following the two lines that are reserved for the register update procedure. the allowed range for the vgp is included between the 0 and 511 video lines. 7.3 cursor 7.3.1 cursor size the cursor is available in different shapes. the shape is selected by the pas[3] cursor-type bit in the ea register. 7.3.2 cursor position the position of the cursor is determined by the most recent write command on the i2c bus. the embedded ram addresses of dynamic convergence correction values correspond di- rectly to grid positions on the screen. they represent cursor positions as well. if the cpv (cursor position vertical) value exceeds the 0...c(hex) range, the cursor is not dis- played. if a new write address is within the accepted grid range (after having exceeded the range), the cursor pattern is re-displayed (unless the cursor display is turned off). pas[3] 0: small cursor 1: large cursor 12 0 1 2 3 4 5 6 visible screen area v-retrace vgp+2 vgd vres
37/83 stv2050a - video pattern generator 7.4 border lines convergence adjustments at the edges of the screen are more difficult because the grid points which are involved are not visible. therefore, additional horizontal and vertical border lines are implemented for making adjustments at these positions. 7.4.1 border lines: left / right the horizontal position of the border lines is programmable by the bph[5:0] bits in the d7 reg- ister. figure 19. border lines note : the bph bit must be smaller than the hgd bit. 7.4.2 border lines: bottom / top the vertical position of the border lines depends on bits bpv[5:0] in register d7. 00h the position of the border lines is identical to the vertical grid lines at horizon- tal grid positions 1 and 15 01h to 1fh the border lines move toward the centre of the screen in increments of bph clock cycles. the range for the shift of the border line is one horizontal grid distance. 00h the position of the horizontal border lines is identical to the horizontal grid lines at posi- tions 0 and 12. 01h to 1fh the horizontal border lines move toward the centre of the screen by bpv video lines. the allowed range for the bpv value is one vertical grid distance. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 15 0 grid bph bph borderlines
38/83 stv2050a - video pattern generator figure 20. vertical border lines no te : the value of the bpv bit must be smaller than that of the vgd bit. 7.5 gain adjustment lines the gain adjustment lines pattern is used mainly for 2 purposes: C to calibrate the convergence currents in order to achieve a consistent geometrical correction on the screens of a series of ptvs, C to have an easy visual adjustment of the interlace mode. the cursor has two different shapes, one for the adjustment of the vertical gain and another for the adjustment of the horizontal gain. the video pattern for the gain cursor is defined in the ea register. 7.5.1 video pattern for horizontal gain cursor the horizontal gain cursor can be used for adjusting the horizontal convergence channels. the video pattern in the odd field is identical to the video pattern of the large cursor displayed at the centre of the visible grid. gcp 0: gain cursor video pattern off 1: gain cursor video pattern on vhv 0: horizontal gain cursor video pattern 1: vertical gain cursor video pattern 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 v-gridlines border lines bpv bpv
39/83 stv2050a - video pattern generator figure 21. video pattern for horizontal gain cursor note that these controls only modify the video signals. they have no effect on the conver- gence signals. the dedicated controls of the convergence signals are described in section 9.7 "manufacturing, after-sales service, lab trial modes" on page 49 . 7.5.2 video pattern for vertical gain cursor the video pattern for the vertical gain cursor is identical to video pattern for the horizontal gain cursor (displayed at the centre of the visible grid), except for one horizontal line which is added only in the even tv field. figure 22. video pattern for vertical gain cursor odd field even field horizontal grid line number 6 vertical grid line number 8 vertical grid line number 8 horizontal grid line number 6 odd field even field horizontal grid line number 6 additional line vertical grid line number 8 vertical grid line number 8 horizontal grid line number 6
40/83 stv2050a - video pattern generator 7.6 auto-alignment pattern the auto-alignment pattern is a rectangular, highlighted part of a screen with a constant brightness (horizontal brightness). see figure 23 "auto-alignment video pattern" on page 40 . the on/off is controlled by the pas[4] bit in the ea register the size and the position of the pattern can be controlled by the eb and ec registers. the pat- tern is defined by its horizontal and vertical start and stop values: ho1, hg1, ho2, hg2, vo1, vg1, vo2 and vg2. offset position values must be one grid distance smaller than the vertical grid numbers for start or stop positions. figure 23. auto-alignment video pattern pas[4] 0: auto-alignment pattern off 1: auto-alignment pattern on hg1[3:0] grid number of horizontal pattern start ho1[5:0] offset of horizontal pattern start (number of clock cycles, 1 grid max.) hg2[3:0] grid number of horizontal pattern end ho2[5:0] offset of horizontal pattern end (number of clock cycles, 1 grid max.) vg1[3:0] grid number of vertical pattern start vo1[5:0] offset of vertical pattern start (number of video lines, 1 grid max.) vg2[3:0] grid number of vertical pattern end vo2[5:0] offset of vertical pattern end (number of video lines, 1 grid max.) vo1 ho1 gridline hg1 gridline hg2 gridline vg1 gridline vg2 vo2 ho2 autoalignment pattern
41/83 stv2050a - video pattern generator the pattern may be defined so that an end value is less than the start value. in this case, the window will wrap around through the retrace without any interruptions (two or four rectangles will be highlighted on the screen). the auto-alignment pattern signal is influenced by the horizontal or vertical blanking function.
42/83 stv2050a - blanking of video signals 8 blanking of video signals the output of the rgb signals can be set to 0v during the horizontal and vertical retrace. the function is controlled by the d6 register. the horizontal and vertical retrace blanking function can be enabled independently. 8.1 horizontal blanking the hbe bit in the d6 register is used to enable/disable the horizontal blanking. the start and end edge positions are determined by the hvb[5:0] bits in the d6 register. if the horizontal blanking is enabled, the video outputs are set to 0v from the hvb clock cycles before grid line number 15 until the hvb clock cycles after grid line number 1. the useful range for the hvb is one horizontal grid distance. this function is similar to the border line function. if 0 is programmed, grid lines no. 15 and no. 1 are not blanked. figure 24. horizontal grid lines note : if the hvb values are greater than the hgd values, unexpected effects will appear on the screen. 8.2 vertical blanking the enable/disable control is the vbe bit in the d6 register. the start and end edge positions are determined using the vvb[5:0] bits in the d6 register. the video blanking function ends when the programmed number of vvb video lines, following vertical grid line no. 0, are finished and the next video line following the end of the dac retrace mode (dct) has begun. the vvb range is one vertical grid distance. the function works the same as the border line function. if 0 is programmed, grid lines no. 0 and no. 12 are not blanked. if the values pro- hbe 0: horizontal blanking off 1: horizontal blanking on vbe 0: vertical blanking off 1: vertical blanking on 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 0 horizontal grid lines hvb 15 0v dac output 0v dac output hvb hvb hvb 14
43/83 stv2050a - blanking of video signals grammed for vvb are greater than those of the vgd, unexpected effects will appear on the screen. figure 25. vertical blanking 8.3 blanking for auto-alignment pattern the blanking for the auto-alignment pattern and for the other video pattern are linked to the same timing which is defined by the hvb and vvb bits as described in the following sections. 8.4 fast blanking the fblk pin is used to provide a fast switching signal that selects the source of the video signal to be displayed on the screen. features are controlled by the d7 register. hae 0: horizontal blanking off 1: horizontal blanking on vae 0: vertical blanking off 1: vertical blanking on sta 0: fblk depends on the tvh, tvv and fas bits (see below) 1: fblk is forced to 1, if a pattern color is enabled by the cov bits. (refer to section 7.1.1 "pattern selection" on page 33 ) tvh blanking of tv picture in horizontal direction 0: blanking off 1: blanking on 12 0 1 2 3 4 5 6 7 8 9 10 11 12 0 v-gridlines vvb vvb v blank stop v blank start
44/83 stv2050a - blanking of video signals the tvh and tvv bits are designed to be used, for example, in front projection applications. they are used to cut off tv video information at the left and right edges, as well as at the top and the bottom of the projection area that belongs to the overscan region in standard tv sets. tvv blanking of tv picture in vertical direction 0: blanking off 1: blanking on fas 0: normal tv picture only 1: the normal tv picture is overlapped by the video pattern
45/83 stv2050a - convergence 9 convergence the stv2050a generates convergence values from parameters which are stored in the em- bedded ram after having being loaded down from the eeprom. these parameters can be: C common for the entire screen area for each color. they are called common values. they are used for global adjustments, as they have the same effect on all the convergence values of the same color and in the same direction (horizontally or vertically). they are used mainly: C to pre-adjust the geometry and convergence, as well as to reduce the necessary action on each separate point, C to compensate the tolerances of the offset and gain for the external components. C dedicated to each value of the net of 16 points horizontally by 13 points horizontally. they are called dynamic values, C added as an offset frame by frame (interlacing), C forced to special values in alignment modes or during startup and security modes. figure 26. convergence values computation path 9.1 global adjustments - common parameters three sets of parameters are available for each red, green and blue channel for each hori- zontal and vertical direction: C position offset, C gain correction, C offset canceller. dynamic values position offset ("static") e1 , e2 gain correction coarse : e0 fine : d0, d1 field offset canceller d2, d3 to convergence outputs common values interlace da measuring e8 calibration dc, dd
46/83 stv2050a - convergence 9.1.1 position offset (also called static) this value is added to each dynamic value of the corresponding channel. it is used to reach an optimal dynamic value range, and to make a first rough correction. e1 register: horizontal e2 register: vertical the position offset values are in two's complement. 9.1.2 gain correction this gain value is applied to the sum of the dynamic value and the position offset (see figure 26 "convergence values computation path" on page 45 ). it is mainly used for compensating the amplification spread of the external components. (also refer to figure 31 "electrical loop block diagram" on page 55 ). the gain value is divided into 2 ranges, coarse and fine correction. e0 register: coarse d0 register: fine horizontal d1 register: fine vertical srh[7:0] red channel sgh[7:0] green channel sbh[7:0] blue channel srv[7:0] red channel sgv[7:0] green channel sbv[7:0] blue cha nnel rch[3:0] red horizontal rcv[3:0] red vertical gch[3:0] green horizontal gcv[3:0] green vertical bch[3:0] blue horizontal bcv[3:0] blue vertical rfh[7:0] red channel gfh[7:0] green channel bfh[7:0] blue channel rfv[7:0] red channel gfv[7:0] green channel bfv[7:0] blue channel
47/83 stv2050a - convergence 9.1.3 field offset canceller this offset value is totalled after the gain correction. its purpose is mainly to cancel the differ- ential offset between all channels (see refer to section 11 "electrical loop" on page 55 ). d2 register: fine horizontal d3 register: fine vertical the field offset values are in two's complement. note : during the vertical retrace, the field offset canceller values are the only correction values available on the convergence outputs. refer to section 9.6 "normal tv operation mode" on page 48 . 9.2 dynamic values dynamic values are stored in register addresses 00 to cf in the three red, blue and green banks. for their allocation, refer to section 4.1 "convergence correction values" on page 18 . the dynamic values can be adjusted from -512 to +511 9.3 interlace the interlace correction value is defined by the icv[5:0] bits in the da register. this value is added to each convergence value in the field chosen by the ifa bit in the da reg- ister. the interlace mode is enabled by the iie bit in the da register. org[7:0] red channel ogh[7:0] green channel obh[7:0] blue channel orv[7:0] red channel ogv[7:0] green channel obv[7:0] blue channel binary code msb --> lsb -512 '00 0000 0000' 0 '10 0000 0000' +512 '11 1111 1111' iie 0 = no interlace 1 = interlace mode
48/83 stv2050a - convergence 9.4 calibration calibrations can be carried out during manufacturing, or during the normal tv operating mode using the automatic self-alignment procedure via the electrical loop. refer to section 11 "electrical loop" on page 55 . 9.5 interpolation the 10-bit dynamic correction values are expanded by interpolation to 14 precision bits. the interpolation of the correction values stored in the embedded ram produces correction values for the lines between the grid lines. 9.5.1 vertical filter a vertical interpolation is performed by the stv2050a in order to provide a smooth correction transition between the stored points. a complex algorithm is implemented in order to improve the interline geometrical aspect, even when not aligned during chassis production or by the end user. 9.5.2 horizontal filter for each of the three convergence correction channels, an interpolation filter is implemented to calculate the correction values between horizontally-adjacent correction values. different configuration options are programmable using the d8 register. the positions of the calculated additional correction values are timed independently for the visible grid and the retrace grids. since operating the filters will increase the dac frequency by a factor of 2 and 4 respectively, it may be necessary to switch off the filters during the horizontal retrace if the retrace time is short and the line frequency is high. in this case, the filter input data, coming from the vertical interpolation, will be fed directly to the convergence dacs. in any case, this data is processed by the filters in parallel to avoid any discontinuity when the filters are switched back into the data paths. 9.6 normal tv operation mode the following bits must remain at logical 1 in the e3 register as defined by the default values during reset: C the cdo bit (refer to section 9.8 "convergence outputs" on page 51 ), hif[1:0] 00: filter is not active 11: filter is not active 01: filter is a 3-tap fir filter (2 values per grid) 10: filter is a 5-tap fir filter (4 values per grid) fso 0: filter is switched off during horizontal retrace 1: filter is running continuously
49/83 stv2050a - convergence C the cdn bit (refer to section 9.7 "manufacturing, after-sales service, lab tri- al modes" on page 49 ). during normal operation mode, the convergence outputs deliver a signal computed as shown in figure 26 "convergence values computation path" on page 45 . however, during the convergence frame retrace defined by the dcb and dct values as de- scribed in section 5.4.4 "convergence correction frame retrace" on page 26 , only the field offset canceller values are output. this is used to reduce the power in the convergence ampli- fiers. 9.7 manufacturing, after-sales service, lab trial modes 9.7.1 output of field offset values this mode is used to output the field offset values defined in the d2 and d3 registers. it is controlled by the cdn bit in the e3 register. 9.7.2 gain and offset measuring line this mode is used as a manual control of the measuring line used, for example, in the elec- trical loop. (refer to section 11.1 "principle of operation" on page 55 .) during the gain measuring line: C the dynamic values are replaced for each channel by the crh[7:0] and crv[7:0] bits for red, cgh[7:0] and cgv[7:0] bits for green and cbh[7:0] and cbv[7:0] for blue in the dc and dd registers for horizontal and vertical values, respectively, C the polarity of these latter values may be changed using the pmh and pmv bits in the d5 register for horizontal and vertical values, respectively, C the gain value is stored in the e0 register for the coarse value, but the fine values are stored in the mvr[7:0] bits for red, mvg[7:0] bits for green and mvb[7:0] bits for blue in the e8 reg- ister. during field offset measuring lines, the value applied to the dacs for each channel are given by mvr[7:0] for red, mvg[7:0] for green, mvb[7:0] for blue in register e8 the manual measuring line mode is enabled using the mle bit in the d5 register. this may be programmed when the measuring line is inserted using the mln[8:0] bits in the d5 register. this signal is made available on pin 75 (mlin). cdn 0: offset values 1: normal operation mle 0: manual measuring line disabled 1: manual measuring line enabled
50/83 stv2050a - convergence the insertion type is selected using the gos bit in the d4 register. the direction is selected by the hvm bit in the d4 register. 9.7.3 gain cursor mode see figure 27 "gain cursors" on page 51 . this mode is normally used in conjunction with the corresponding video pattern. (refer to sec- tion 7.5 "gain adjustment lines" on page 38 ). the stv2050a can generate a special convergence signal (cursor) controlled by the gcd bit in the e3 register. the cursor action is selected by the dhv bit in the e3 register. during the gain measuring lines: C the dynamic values are replaced for each channel by the crh[7:0] and crv[7:0] bits for red, cgh[7:0] and cgv[7:0] bits for green and cbh[7:0] and cbv[7:0] for blue in the dc and dd registers for horizontal and vertical values, respectively. C the polarity of these latter values may be changed using the pmh and pmv bits in the d5 register for horizontal and vertical values, respectively. C the gain value is stored in the e0 register for the coarse value, but the fine values are stored in the mvr[7:0] bits for red, mvg[7:0] bits for green and mvb[7:0] bits for blue in the e8 reg- ister. in vertical cursor mode, the resulting values applied to the dacs are first positive, then in- verted on the following tv line. in horizontal mode, the values are inverted at each tv line. 9.7.4 field offset cursor mode see figure 27 "gain cursors" on page 51 . this mode is normally used in conjunction with the corresponding video pattern. (refer to sec- tion 7.5 "gain adjustment lines" on page 38 .) gos 0: field offset canceller 1: gain compensation hvm 0 = vertical 1 = horizontal gcd 0 = cursor off 1 = cursor on dhv 0 = horizontal cursor 1 = vertical cursor
51/83 stv2050a - convergence the stv2050a can generate a special convergence signal (cursor) controlled by the gcd bit in the e3 register. tthe cursor action is selected by the dhv bit in the e3 register. during field offset measuring lines, the values applied to the dacs for each channel are given by the mvr[7:0] bits for red, mvg[7:0] bits for green and mvb[7:0] bits for blue in the e8 reg- ister. in vertical cursor mode, the resulting values applied to the dacs are first positive, then in- verted on the following tv line. in horizontal mode, the values are inverted at each tv line. figure 27. gain cursors when using this mode, the stv2050a must be correctly set in order to recognize the inter- laced field. the iie bit in the da register must be set to 1. 9.8 convergence outputs the values of the six convergence channels are converted by 14-bit dacs with a differential current output. gcd 0 = cursor off 1 = cursor on dhv 0 = horizontal cursor 1 = vertical cursor n' -a +a vertical gain adjustment horizontal gain adjustment n' n'+4 n'+2 n'+1 n'+3 n+1 n+3 n n+4 n+2 - a + a n+5 middle of video grid (odd) n n+1 (even) (even) (even) (even) (odd)
52/83 stv2050a - convergence figure 28. convergence channel structure calibrated sources are used to generate the reference current for all convergence and focus dacs. the reference current is defined as . (refer to section 13 "current reference" on page 61 .) the outputs can be disabled using the cdo bit in the e3 register. notes : 1. the cdo bit is a common control for the convergence and the focus outputs. 2. the cdn bit must be set to 1 for normal operation. refer to section 9.7 "manufacturing, after- sales service, lab trial modes" on page 49 . in order to perform a soft start of the convergence to avoid damaging the amplifiers, a soft switch on of the dacs is carried out digitally by applying a reduced digital gain (reduction by factor 2) for at least 1 field after the dacs have been switched on from high impedance to normal operation (using the cdo bit) or when the dacs have been previously switched to the offset values by the slave bus. cdo 0: high impedance 1: normal operation. convergence value compensation differential control of convergence current outputs daxx dnxx + - iref 2 ---------
53/83 stv2050a - dynamic focus 10 dynamic focus 10.1 parabola curve the focus function delivers a current with 6-bit resolution, which is constant for horizontal lines. in vertical direction, the current has the shape of a second order parabola. the parabola is defined by three points, fv1, fv2 and fv3, whose values correspond to the fv1[5:0], fv2[5:0] and fv3[5:0] values which are stored in the de register. the position of these last 3 points is a multiple of (vgd+1). see figure 29 "focus parabola" on page 53 . the parabola is therefore linked to the value of the vertical grid distance. figure 29. focus parabola the focus dac will provide a programmable constant value in the fvr[5:0] bits in the de reg- ister at the bottom of the screen and during vertical retrace. the start of the retrace value is programmable using the fsb[7:0] bits in the da register as shown above. the position is indicated by the vfp[8:0] bits in the d9 register. notes : 1. if vres becomes active before the number of lines for the fsb have been counted, the parabola will be terminated and replaced by the fvr retrace value. 2. the hardware is not equipped with a safeguard device against dac range overflow. this may occur if the fv2 bit is near the max. positive or negative value and the parabola is not symmetrical to the fv2 centre value. also, large values for the fsb have to be taken into account. x/2 0 fv1 fv2 fv3 fvr 32 48 16 63 0 vfp+3 0 field n field n+1 x tv lines fsb y x = 12 * (vgd + 1) y = 11 * (vgd + 1) focus dac vertical retrace ( vres ) fv1
54/83 stv2050a - dynamic focus 10.2 focus outputs the focus output signal is delivered on the focs pin. this output is normally used together with a static reference generated on the focr pin. this static reference corresponds to the mid-range code value. figure 30. focus outputs focus reference level stv2050a - + 6-bit dac focs focr focus waveform generator
55/83 stv2050a - electrical loop 11 electrical loop 11.1 principle of operation it is possible to multiply convergence values with a digital gain value and add a digital offset value to the convergence values during convergence signal processing (see figure 26 "con- vergence values computation path" on page 45 ). this can be used to compensate offset cur- rent and gain differences of the external convergence amplifiers. however, aging and temper- ature can cause drifting, and the correction values may have to be adjusted. in order to avoid a manual after-sales re-alignment, the stv2050a can perform an automatic update of the field offset canceller values, as well as for the gain correction values. for this purpose a measuring line in the invisible part of the picture (for example, during the frame retrace procedure) can be used to provide measurement values at convergence out- puts. (refer to figure 31 "electrical loop block diagram" on page 55 .) offset current and gain values of the amplifiers are measured with comparators, which are connected to the pora, porb, porc port pins of the ic. the reference values are available on the ogah and ogav pins. figure 31. electrical loop block diagram once the measurement is carried out, the convenient field offset canceller and gain compen- sation corrections for the convergence values can be controlled by either an embedded process (internal loop), or by an external mcu, when the internal loop is disabled. the loop is activated using the stl bit in the e3 register. stl 0 = internal loop enabled 1 = internal loop disabled dac electrical loop convergence processing amplifier yoke sense- resistor measuring line ogah,ogav pora porb porc
56/83 stv2050a - electrical loop a measuring line is inserted in each frame for measuring either the offset or the gain of the am- plifiers. therefore, the compensation procedure has to run through the offset/gain measure- ment and horizontal/vertical channels sequentially. the right comparator is activated by the timing of the signals on the ogav and ogah pins. (refer to figure "" on page 8 ). programming is possible when the measuring line is inserted using the mln[8:0] bits in the d5 register. 11.2 loop parameter register parameters for the internal loop circuit are defined in the df register. offset and gain compensation can be enabled separately using the ole and gle bits. if the fin bit in the df register is high, the device only carries out one single measurement during the first time that the compensation is carried out. the comparison sign of the pora, porb and porc pins can be programmed by using the dio bit for the offset and the dig bit for the gain in the df register. the number of measurements that are evaluated for selecting a new compensation value is determined by the nom[7:0] bits in the df register. number of deviating results among the nom measurements that do not lead to a change of the actual compensation value is determined by the tol[7:0] bits in the df register. 11.3 loop status register all functions for the port control and the gain range control that are influenced by the compen- sation loop are available via the i2c e4 register. this register is used if the gain and/or offset loop is handled by an external mcu. the ic internal loop has its own registers which are mapped to the e4 address in the event of read access to this address. C the pia, pib and pic bits indicate the status of the pora, porb and porc ports respec- tively. C the elo bit indicates if the electrical loop is ready (=1) or not (=0). ole 0 = offset loop activated 1 = offset loop disabled gle 0 = gain loop activated 1 = gail loop disabled fin 0: no exception for first loop cycle 1: first loop cycle with fixed parameters for fast operation dig 0: the level on the port is high if the convergence current is too high 1: the level on the port is low if the convergence current is too high.
57/83 stv2050a - electrical loop 11.4 operation of the electrical loop the electrical loop is started by the stv2050a reset procedure following the readout of the eeprom and the updating of the ic registers once the convergence outputs are enabled (the s02 and s03 bits in the e3 register are set to 1). if loop operation is enabled with the ole and gle bits, the loop sets the ru1 and ru2 bits to low in the ef register which disables the ram updating the d0*...d3* and e4 registers. the elo bit in the e4 register is set to high by the ic reset, which indicates to external mcus that the first offset/gain compensation is not yet completed. if enabled, the offset and the gain compensation procedures are repeated endlessly. if the offset compensation is enabled by the ole bit, the measuring line is switched to offset mode (gos = 0) and the compensation procedure is done sequentially for horizontal (hvm=1) and vertical (hvm=0) channels. if the gain compensation is enabled by the gle bit, the measuring line is switched to gain mode (gos=1) and the compensation procedure is carried out for horizontal (hvm=1) and vertical (hvm=0) channels. when the compensation for all channels is completed for the first time, the elo bit is set to low in order to supply this information to external mcus. the activity of the internal loop circuit has to be interrupted if the convergence dacs are dis- abled (which can be detected at the s02 and s03 bits) or if the stl bit in the e3 register is high or if the gle and the ole bits are low. 11.5 output/input pads 5 pins are dedicated for the electrical loop: pora, porb, porc, ogah and ogav. however, these pins can be used for other purposes and are all programmable. 11.5.1 pora, porb and porc pins these pins can be set as either input or output pins using the corresponding pda, pdb and pdc bits in the e4 register. if the ports are set as an input, the value on the port is sampled with the timing set by the plt bit in the e4 register. if the ports are set as an output, the value on the port is given by the value of the poa, pob or poc bits in the e4 register. pda, pdb or pdc 0 = input 1 = output plt 0: by the system clock 1: at the end of the measuring line
58/83 stv2050a - electrical loop 11.5.2 ogah and ogav pins the ogah (pin 57) and ogav (pin 58) pins are multi-level output pins. in addition to the normal digital output function (logical 0 and 1), they can drive a very stable current and can be switched to high impedance. the stable current and the high impedance can be used to generate the reference voltage across a grounded resistor for the gain and offset detection comparators. each pad is controlled by two corresponding bits in the e4 register. figure 32. e4 register attention : the ogav and ogah pins cannot both drive i ref at the same time . gah[1:0] 0 0 = high impedance 0 1 = 0 1 0 = iref 1 1 = 1 gav[1:0] 0 0 = high impedance 0 1 = 0 1 0 = iref 1 1 = 1 ogah ogav 2 gav control bit 1 gav control bit 2 gah control bit 1 gah control bit 2
59/83 stv2050a - optical loop 12 optical loop 12.1 principal of operation figure 33. optical loop the stv2050a can deliver a dedicated video pattern known as an auto-alignment pattern. this pattern is rectangular-shaped, and its width, height and brightness are programmable. refer to section 7.6 "auto-alignment pattern" on page 40 . the presence or absence of this pattern can be detected by optical sensors; for example, by a camera in the production line, or photo detector diodes placed around the projection screen. the stv2050a can read the status of the sensors within a programmable time limit. the re- sults are made available in the e5 register, allowing the mcu to run a routine for making the necessary corrections. two pins are dedicated to the optical loop: C the oppt pin is a port normally used as an output, and can deliver a logical electrical signal with a programmable time limit. C the opti pin is an input port for logical 0 or 1 levels. this port is sampled by the stv2050a to indicate the status of the sensor. 12.2 optt sensor port control the optt sensor port can be programmed as an input or as an output by the ods in the e5 register. ods 0 = optt is an input 1 = optt is an output optt rgb opti i2c p sensor h/v grid ti ming stv 2050d offset static gain dynamic h v stv2050a
60/83 stv2050a - optical loop 12.2.1 optt pin used as an input the status of optt is available in s05 in register e5. 12.2.2 optt pin used as an output the optt output can either be forced to the electrical 1 level, or can be programmed in the same way as the auto-alignment pattern. this is carried out by the oos bit in the e5 register. in the latter case, the timing of the oppt signal typically overlaps the auto-alignment pattern. the final signal is used to control the opti and optt port functions. the timing for the signal is defined by the ed and ee registers. offset values larger than one grid distance or invalid vertical grid numbers for start or stop po- sition will cause unexpected results at the optt_pattern signal. the optt_pattern signal is not influenced by the horizontal or vertical blanking function. 12.3 opti sensor status port the level applied to the opti pin can be read using the s11 bit in the e5 register. the opti level can be anded with the window defined on the optt using the opi in the e5 register. s05 0: < 0.7 v on optt 1: > 2.6 v on optt oos 0: data output = the odt bit in the e5 register 1: programmable timing hg3 grid number of horizontal start ho3 offset of horizontal start (number of clock cycles, 1 grid max.) hg4 grid number of horizontal end ho4 offset of horizontal end (number of clock cycles, 1 grid max.) vg3 grid number of vertical start vo3 offset of vertical start (number of video lines, 1 grid max.) vg4 grid number of vertical end vo4 offset of vertical end (number of video lines, 1 grid max.) opi 0: s11 = opti and window 1: no windowing
61/83 stv2050a - current reference 13 current reference the stv2050a delivers accurate and stabilized currents used to drive the convergence and focus functions. it has an embedded voltage reference (band gap), which is used to generate a reference current (i refn ) the nominal voltage on the refn pin is 500 mv. the irefn current must be adjusted to 500 ua. this is obtained by using a temperature stable external resistor of 1 k w . the reference voltage may be adjusted by using the bga[4:0] bits in the d5 register. figure 34. current and voltage references stv2050a - + refc band gap voltage reference refn v refn i refn bga[4:0]
62/83 stv2050a - securities 14 securities 14.1 overview the stv2050a can prevent overcurrents in the convergence coils, or poor programming, using the following controls: C at power-on reset, or after a reset, all analog outputs are disabled, and the stv2050a waits until at least 2 pulses of each horizontal and vertical signals are received. C as long as the internal set-up is not achieved, the outputs remain disabled. the setup dura- tion is typically 2 field periods. C when setup is achieved, the dac outputs are not fully released and the values are reduced 50% during one field. C the transfer between eeprom and embedded ram of the data stored in register e9 is pro- tected by a hamming code. C during normal operating mode, each convergence value stored in the embedded ram is checked by a parity checker before it is applied to the dacs. if a parity error occurs, the s19 bit in the e3, e4, e5 and e9 resisters are set as follows. an error flag is available in read mode through the slave i2c bus. 14.2 hamming encoding the e9 register contains certain values which are protected by a hamming code: :eepro- madd[2:0], ads[1:0] and rwm[2:0]. the hamming code is stored in the ham[3:0] bits in the e9 register. s19 0: parity ok 1: parity error msb lsb d0 byte d1 byte d2 byte add 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 e9 eepro- madd [2:0] x x x ads[ 1:0] rwm [2:0] x ham[3:0] x x x x x x x x
63/83 stv2050a - boot sequence to initiate access to an eeprom, the mcu must generate this code. a simple method is to store the values in a single temporary byte tmp[7:0] and to compute each bit of the hamming ham[3:0] bits as follows: ham[0] = tmp[4] xor tmp[3] xor tmp[2] xor tmp[1] xor tmp[0] ham[1] = tmp[6] xor tmp[5] xor tmp[4] xor tmp[2] xor tmp[0] ham[2] = tmp[7] xor tmp[5] xor tmp[2] xor tmp[1] ham[3] = tmp[7] xor tmp[6] xor tmp[4] xor tmp[3] 14.3 security output the pout output can be considered as an open drain from a functional point of view, that is to say that it can have two electrical states: high impedance or pull-down to the ground. it can be used, for example, to force all external amplifiers to a secured biasing. refer to figure "" on page 8 . the electrical status of this output is controlled by the ppl bit in the e3 register. during normal operation it is pulled down to ground: C if the stv2050a detects a malfunction such as a parity check error or power on reset error. C until the power-on reset is released. otherwise, pout is set to high impedance. in this case, the logical status of the pout pin can be read using the s02 bit in the e3 register. 15 boot sequence at startup, or following a reset on pin 13, the stv2050a will: C immediately disable all the outputs (forced to the zero current value, in order to protect the application against over-currents in the coils for example), msb lsb tmp byte 7 6 5 4 3 2 1 0 eepromadd [2:0] ads[1:0] rwm [2:0] ppl 0: normal operation 1: high impedance
64/83 stv2050a - ic status registers C wait until the hsync and vsync signals are available on pins 27 and 28 respectively. (at least 2 vsync pulses are required). if one signal is missing, the stv2050a remains in stand-by mode. C use the i2c master to read the eepromadd[2:0] data bits in the eeprom having the hard- ware address 010 (bin). the eepromadd[2:0] bits represent the address of the eeprom which will be used to setup the stv2050a during the boot sequence, note : this is particularly suitable when it is necessary to recover the last configuration used before switch- ing off for example. C use the i2c master to download all convergence data and registers (from the selected eep- rom, as explained before), C wait for up to 2 fields after all the data has been downloaded and enable the outputs. 16 ic status registers some registers of the stv2050a can be read via the i2c slave bus in order to indicate the up- dated status of the ic. the update is enabled using the rue bit in the ef register. the update timing of registers d0 to d3 is determined by the ru1 bit in the ef register. the update timing of the e4 register is determined by the ru2 bit in the ef register. the s01 bit in the e3 or e4 or e5 or e9 registers: C power-on reset status the s02 bit in the e3 register: C security output (pout) status rue 0: no update 1: update enabled ru1 0: no update 1: update after vertical reset ru2 0: no update 1: update after vertical reset s01 0: reset successfully achieved 1: reset ongoing s02 0: 0 (pull down to ground) 1: high impedance
65/83 stv2050a - bus expander 17 bus expander the 8 digital outputs (tbu0 to tbu7) can be used as a bus expander (output only) if dte reg- ister ef is set to "1". each output can be set to logical 0 or 1 using the corresponding tbu[7:0] bits in the fe register. 18 absolute maximum ratings 19 recommanded operating conditions 20 electrical characteristics t a = 25 c, unless otherwise specified. v dd = 3.3 v, external components as shown in figure 4 "application circuit" on page 8 . 20.1 general 20.2 current reference symbol parameter min. typ. max. unit v ddmax 3.6 v t amb ambient temperature operating range 10 70 c t store storage temperature range -25 125 c symbol parameter min. typ. max. unit v dd power supply voltage 3.0 3.3 3.6 v p tot power dissipation 450 mw parameter min. typ. max. unit conditions average current on 100 ma parameter min. typ. max. unit conditions adjustable voltage range 0.45 v bga[4:0] = 00 (hex) 0.55 v bga[4:0] = 1f (hex) temperature drift (10c to 70c) 45 | ppm / c
66/83 stv2050a - electrical characteristics 20.3 video pattern outputs 20.3.1 dacs for rgb 20.3.2 fblk output 20.4 focus dacs 20.4.1 focus reference parameter min. typ. max. unit conditions resolution 4 bit output voltage 70 200 mv code 0000b applied, i out < 0.1 ma 0.4 0.6 0.8 v code 0001b applied, i out < 0.1 ma 1.9 2.3 2.7 v code 1111b applied, i out < 0.5 ma dnl 0.1 0.25 lsb except code 0000b inl 0.2 0.5 lsb except code 0000b matching between dacs 3 10 % max. code applied; ref signal for 10% is the channel of rgb with the max signal value rise time (10...90%) 5 20 ns from code 0(hex) to f(hex) fall time (10...90%) 2 10 ns from code f(hex) to 0(hex) delay between video dacs (50%) 4ns parameter min. typ. max. unit conditions output voltage low 0.4 v 2 ma input output voltage high 2.4 v 2 ma output rise/fall time (10...90%) 10 ns 15 pf load symbol parameter min typ max. unit conditions i focrfocr focus reference cur- rent on pin focr -7 +7 % temperature drift of output current 150 | ppm / c 0c to 70c 3 4 -- - i refn
67/83 stv2050a - electrical characteristics 20.4.2 focus signal 20.5 convergence dacs 20.6 pll 20.7 master i2c time base symbol parameter min typ max. unit conditions highest output cur- rent on pin focs -7 +15 % max. code (3f hex) applied, v out = 0.5 v smallest output cur- rent on pin focs 0.5 5 a min. code (00 hex) applied output current match- ing on pin focs ver- sus focr -5 +5 % mid-code (20 hex) applied, v out = 0.5 v focus dac dnl (focs pin) 0.2 0.7 lsb focus dac inl (focs pin) 0.2 1 lsb operating range 1.5 v voltage rise/fall time (10...90%) 2ms 1.33 k w , 15 pf load parameter min. typ. max. unit conditions resolution 14 bit max. output current -0.5 2. irefn +0.5 % max. code applied min. output current 1 lsb code 00h applied operating range 0 100 500 mv dnl 1 2 lsb max. v out = 100 mv inl 2 4 lsb max. v out = 100 mv autocalibration adjustment refresh interval 5ms horizontal line frequency 15 50 khz horizontal line retrace time tbd 12 s internal parasitic capacitance on each dac output 15 pf signal / noise ratio 90 db 300 hz to 500 khz, df = 1 khz max. code (3fff) temperature drift of full scale output current 35 60 | ppm / c | including bandgap temperature drift parameter min. typ. max. unit conditions number of system clock pulses per line 250 512 parameter min. typ. max. unit conditions scl frequency 65 85 khz recommended filter 3 2 -- - i refn
68/83 stv2050a - electrical characteristics 20.8 horizontal and vertical synchronization inputs 20.9 tbu outputs 20.10 electrical loop pads notes : 1. pora..c input level can be latched in measuring line or with sys. clock. 2. pora..c and optt input have digital inputs. 3. opti is only an input pin. 4. mlin is only an output pin. it sends a pulse during the measuring line (m_line, see gain range control). the signal can be used to gate the comparators at the port a...c pins or to switch time constants. parameter min. typ. max. unit conditions threshold v up 1.4 1.8 v threshold difference v down - v up 0.130 v temperature drift of v up 90 mv const. supply voltage ambient temp. 10- 70c parameter min. typ. max. unit conditions output voltage at low level (logical 0) 0.4 v 2 ma input current output voltage at high level (logical 1) 2.4 v 2 ma output current parameter min. typ. max. unit conditions output voltage at low level (logical 0) 0.4 v 2 ma input current output voltage at high level (logical 1) 2.4 v 2 ma output current leakage current at high impedance 1a 0 < v out < v dd output current (gah = 10 bin.) -0.5 irefn +0.5 % 2 k w load, max voltage = 1v temperature drift of ref cur- rent 60 ppm /c 2 k w load, including the temperature drift of the bandgap input logical 0 0.7 v input logical 1 2.6 v
69/83 stv2050a - package mechanical data 21 package mechanical data figure 1. 80-pin plastic quad flat package pqfp080 dim mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.904 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.40 0.724 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.80 0.031 k 0 7 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 number of pins n80 nd24ne16 0.10mm .004 seating plane
70/83 stv2050a - electrical pin configuration 22 electrical pin configuration pin name pin name 19 vccd 41 gndh 26 vccf 47 gnda 42 vcch 67 gndc 44 vccg 50 vcca 62 vccb 70 vccc pin name pin name 8 sdai 7 sdao 9 scls 11 test 13 rest 27 synh 28 synv 71 ads0 72 opti gnd vdd gnd vdd gnd vdd vdd gnd vdd gnd
71/83 stv2050a - electrical pin configuration pin name pin name 54 refn 57 ogah 58 ogav pin name pin name 1 sdam 3 gndq 2 sclm 15 gndn 10 vblk 30 gndl 33 tbu0 34 tbu1 35 tbu2 36 tbu3 37 tbu4 38 tbu5 pin name 39 tbu6 5 vccq 40 tbu7 6 vcck 74 optt 12 vccn 75 mlin 78 porc 79 porb 80 pora pad gnd vdd pad vdd gnd vdd gnd vdd gnd vdd gnd vdd vdd gnd gnd
72/83 stv2050a - electrical pin configuration pin name pin name 31 vccj 4 gndk 32 vccl 20 gndd 73 vccm 29 gndj 59 gndb 76 gndm gnd vdde gnd vdd
73/83 stv2050a - i2c bus register variable glossary and register location 23 i2c bus register variable glossary and register location a acl auto calibration system clock............................................................................d8 acw auto calibration window.....................................................................................d8 ads adjustment data set ...........................................................................................e9 afs number of calibrated cells per line......................................................................d8 aie autoincrement enable.........................................................................................e7 ams autocalibration mode selection...........................................................................d5 asp autocalibration start position ..............................................................................d8 b bch coarse gain of blue horinzontal .........................................................................e0 bcv coarse gain of blue vertical................................................................................e0 bfh blue fine gain correction horizontal ...................................................................d0 bfv blue fine gain correction vertical .......................................................................d1 bga bandgap adjustment ..........................................................................................d5 bph border position horizontal ..................................................................................d7 bpv border position vertical.......................................................................................d7 c cbh calibration value blue horizontal ....................................................................... dc cbs color bank selection...........................................................................................e7 cbv calibration value blue vertical ........................................................................... dd cdn offset values on convergence.............................................................................e3 cdo convergence and focus output disable...............................................................e3 cgh calibration value green horizontal .................................................................... dc cgv calibration value green vertical ........................................................................ dd cov color selection of video pattern ......................................................................... ea cpv cursor position vertical crh calibration value for red horizontal .................................................................. dc crv calibration value for red vertical....................................................................... dd d dcb dac count bottom............................................................................................. db dct dac count top.................................................................................................. db dhv horizontal or vertical cursor selection.................................................................e3 dig sign of gain comparison..................................................................................... df dio sign of offser comparison .................................................................................. df e elo ............................................................................................................................e4
74/83 stv2050a - i2c bus register variable glossary and register location eeprom addeeprom address ..................................................................................e9 f fas fast blanking enable ..........................................................................................d7 fin fast compensation of electrical loop.................................................................. df fsb focus stop bottom............................................................................................. da fso filter switched off during horizontal retrace .......................................................d8 fv1 focus parabola top value................................................................................... de fv2 focus parabola middle value ............................................................................. de fv3 focus parabola bottom value............................................................................. de fvr focus value during frame retrace ...................................................................... de g gah ogah pin configutation ......................................................................................e4 gau ............................................................................................................................d4 gav ogav pin configutation................................................................................. d4,e4 gax ............................................................................................................................d4 gay ............................................................................................................................d4 gcd measurement cursor on dacs on/off ............................................................e3 gch coarse gain of green horinzontal.......................................................................e0 gcp gain video pattern enable ................................................................................. ea gcv coarse gain of green vertical.............................................................................e0 gfh green fine gain correction horizontal ................................................................d0 gfv green fine gain correction vertical.....................................................................d1 gle gain loop enable .............................................................................................. df gos gain or offset measurement selection ......................................................... d4,e4 h hae horinzontal autoaligment blanking enable .........................................................d6 ham hamming code ....................................................................................................e9 hbe horizontal blanking enable .................................................................................d6 hdp horizontal dac phase ....................................................................................... db hg1 horizontal aligment pattern start ........................................................................ eb hg2 horizontal aligment pattern end ......................................................................... eb hg3 start of horizontal optical output......................................................................... ed hg4 end of horizontal optical output.......................................................................... ed hgd horizontal grid distance .....................................................................................d8 hgp horizontal grid position ......................................................................................d7 hif horinzontal filter mode .......................................................................................d8 ho1 horizontal aligment pattern start offset.............................................................. eb ho2 horizontal aligment pattern end offset............................................................... eb ho3 offset start of horizontal optical output............................................................... ed ho4 offset end of horizontal optical output................................................................ ed
75/83 stv2050a - i2c bus register variable glossary and register location hrd horizontal retrace distance ...............................................................................d8 hvb horinzontal video blanking position....................................................................d6 hvm horintal or vertical measurement.................................................................. d4,e4 i icv interlace correction value.................................................................................. da ifa interlace field choice ......................................................................................... da iie interlace enable.................................................................................................. da m mle manual measuring line enable...........................................................................d5 mln measuring line number......................................................................................d5 msy ............................................................................................................................e4 mvb measuring value for blue channel.......................................................................e8 mvg measuring value for green channel ....................................................................e8 mvr measuring value for red channel ........................................................................e8 n nom number of measurements.................................................................................. df o obh offset canceller blue horizontal..........................................................................d2 obv offset canceller blue vertical ..............................................................................d3 ods optt port direction selection..............................................................................e5 odt optt output data................................................................................................e5 ogh offset canceller green horizontal .......................................................................d2 ogv offset canceller green vertical ...........................................................................d3 ole offset loop enable ............................................................................................ df oos optt output mode..............................................................................................e5 opi opti windowing ..................................................................................................e5 orh offset canceller red horizontal ..........................................................................d2 orv offset canceller red vertical...............................................................................d3 p pas pattern selection................................................................................................ ea pbh pattern brightness horizontal .............................................................................d6 pbv pattern brightness vertical..................................................................................d6 pda port a direction selection ............................................................................. d4,e4 pdb port b direction selection ............................................................................. d4,e4 pdc port c direction selection ............................................................................. d4,e4 pia status of the port pora......................................................................................e4 pib status of the port porb......................................................................................e4
76/83 stv2050a - i2c bus register variable glossary and register location pic status of the port porc .....................................................................................e4 plt port latch timing ............................................................................................ d4,e4 pmh parity of register dc values ................................................................................d5 pmv parity of register dd values ................................................................................d5 poa port a output data ......................................................................................... d4,e4 pob port b output data ......................................................................................... d4,e4 poc port c output data ......................................................................................... d4,e4 ppl security output enable ........................................................................................e3 prs pll time constant selection................................................................................d5 r rch coarse gain of red horizontal ............................................................................e0 rcv coarse gain of red vertical ................................................................................e0 rfh red fine gain correction horizontal....................................................................d0 rfv red fine gain correction vertical ........................................................................d1 rrp register read pointer.........................................................................................ef rue register update enable ......................................................................................ef ru1 d0 d3 registers update timing.............................................................................ef ru2 e4 register update timing ....................................................................................ef rwm read write mode for eeprom ..........................................................................e9 s s01 power on reset status.........................................................................e3,e4,e5,e9 s02 pout status .......................................................................................................e3 s03 ............................................................................................................................ e3 s05 status of the optt port ......................................................................................e5 s09 read out the horizontal position..........................................................................e5 s10 read out the vertical position..............................................................................e5 s11 status of the opti port .......................................................................................e5 s12 ............................................................................................................................ e5 s13 1st field vertical pulse timing ...............................................................................e6 s14 2nd field vertical pulse timing ..............................................................................e6 s19 status : parity check............................................................................e3,e4,e5,e9 sbh position offset of blue horinzontal ......................................................................e1 sbv position offset of blue vertical ............................................................................e2 sgh position offset of green horinzontal ...................................................................e1 sgv position offset of green vertical..........................................................................e2 srh position offset of red horinzontal.......................................................................e1 srv position offset of red vertical.............................................................................e2 sse soft switch enable ..............................................................................................fe sta force the video pattern fast blanking ..................................................................d7 stl ............................................................................................................................ e3 stx status of transmission with eeprom................................................................e9
77/83 stv2050a - i2c bus register variable glossary and register location t tbu bus expander.....................................................................................................fe te1 ............................................................................................................................ e7 te2 ............................................................................................................................ ef te3 ............................................................................................................................ ef
78/83 stv2050a - index of i2c bus registers 24 index of i2c bus registers a acl ............................................................................................................................... ..............19, 23, 24 acw ............................................................................................................................... ...................19, 24 ads ............................................................................................................................... ..13, 27, 28, 61, 62 afs ............................................................................................................................... ....................19, 24 aie ............................................................................................................................... ......................14, 20 ams ............................................................................................................................... ...................19, 24 asp ............................................................................................................................... ....................19, 24 b bch ............................................................................................................................... ...................19, 45 bcv ............................................................................................................................... ....................19, 45 bfh ............................................................................................................................... ....................19, 45 bfv ............................................................................................................................... ....................19, 45 bga ............................................................................................................................... .............19, 60, 64 bph ............................................................................................................................... ....................19, 36 bpv ............................................................................................................................... ..............19, 36, 37 c cbh ............................................................................................................................... .............19, 48, 49 cbs ............................................................................................................................... ..............15, 16, 20 cbv ............................................................................................................................... ..............19, 48, 49 cdn ............................................................................................................................... .............20, 48, 51 cdo ............................................................................................................................... .............20, 47, 51 cgh ............................................................................................................................... .........................19 cgv ............................................................................................................................... .........................19 cov ............................................................................................................................... .............20, 33, 42 cpv ............................................................................................................................... ..........................35 crh ............................................................................................................................... .........................19 crv ............................................................................................................................... .........................19 d dcb ............................................................................................................................... .........................19 dct ............................................................................................................................... ....................19, 41 dhv ............................................................................................................................... .............20, 49, 50 dig ............................................................................................................................... .....................19, 55 dio ............................................................................................................................... .....................19, 55 e eepromadd ...........................................................................................................20, 27, 29, 61, 62, 63
79/83 stv2050a - index of i2c bus registers elo ............................................................................................................................... ....................20, 56 external pll ............................................................................................................................... ...........14 f fas ............................................................................................................................... ....................19, 43 fin ............................................................................................................................... ......................19, 55 fsb ............................................................................................................................... ....................19, 52 fso ............................................................................................................................... ....................19, 47 fv1 ............................................................................................................................... .....................19, 52 fv2 ............................................................................................................................... .....................19, 52 fv3 ............................................................................................................................... .....................19, 52 fvr ............................................................................................................................... ....................19, 52 g gah ............................................................................................................................... .............19, 20, 57 gav ............................................................................................................................... .............19, 20, 57 gcd ............................................................................................................................... .............20, 49, 50 gch ............................................................................................................................... ...................19, 45 gcp ............................................................................................................................... ...................20, 37 gcv ............................................................................................................................... ...................19, 45 gfh ............................................................................................................................... ...................19, 45 gfv ............................................................................................................................... ....................19, 45 gle ............................................................................................................................... ..............19, 55, 56 gos ............................................................................................................................... .......19, 20, 49, 56 h hae ............................................................................................................................... ....................19, 42 ham ............................................................................................................................... .............20, 61, 62 hbe ............................................................................................................................... ....................19, 41 hdp ............................................................................................................................... ...................19, 23 hg1 ............................................................................................................................... ....................20, 39 hg2 ............................................................................................................................... ....................20, 39 hg3 ............................................................................................................................... ....................20, 59 hg4 ............................................................................................................................... ....................20, 59 hgd ............................................................................................................................... .19, 22, 23, 34, 41 hgp ............................................................................................................................... ...................19, 34 hif ............................................................................................................................... ......................19, 47 ho1 ............................................................................................................................... ....................20, 39 ho2 ............................................................................................................................... ....................20, 39 ho3 ............................................................................................................................... ....................20, 59 ho4 ............................................................................................................................... ....................20, 59 hrd ............................................................................................................................... .............19, 22, 34 hvb ............................................................................................................................... ..............19, 41, 42
80/83 stv2050a - index of i2c bus registers hvm ............................................................................................................................... .......19, 20, 49, 56 i icv ............................................................................................................................... .....................19, 46 ifa ............................................................................................................................... ......................19, 46 iie ............................................................................................................................... .................19, 25, 46 internal pll ............................................................................................................................... ............14 m mle ............................................................................................................................... ....................19, 48 mln ............................................................................................................................... .............19, 48, 55 msy ............................................................................................................................... .........................20 mvb ............................................................................................................................... .......20, 48, 49, 50 mvg ............................................................................................................................... .......20, 48, 49, 50 mvr ............................................................................................................................... .......20, 48, 49, 50 n nom ............................................................................................................................... ...................19, 55 o obh ............................................................................................................................... ...................19, 46 obv ............................................................................................................................... ...................19, 46 ods ............................................................................................................................... ...................20, 58 odt ............................................................................................................................... ...................20, 59 ogh ............................................................................................................................... ...................19, 46 ogv ............................................................................................................................... ...................19, 46 ole ............................................................................................................................... ..............19, 55, 56 oos ............................................................................................................................... ...................20, 59 opi ............................................................................................................................... .....................20, 59 optt_pattern ............................................................................................................................... ..59 org ............................................................................................................................... .........................46 orh ............................................................................................................................... .........................19 orv ............................................................................................................................... ...................19, 46 p pas ............................................................................................................................... ........20, 32, 35, 39 pbh ............................................................................................................................... ....................19, 33 pbv ............................................................................................................................... ....................19, 33 pda ............................................................................................................................... ..............19, 20, 56 pdb ............................................................................................................................... ..............19, 20, 56 pdc ............................................................................................................................... .............19, 20, 56 pia ............................................................................................................................... ............................20
81/83 stv2050a - index of i2c bus registers pib ............................................................................................................................... ............................20 pic ............................................................................................................................... ...........................20 plt ............................................................................................................................... ...............19, 20, 56 pmh ............................................................................................................................... .............19, 48, 49 pmv ............................................................................................................................... .............19, 48, 49 poa ............................................................................................................................... .............19, 20, 56 pob ............................................................................................................................... .............19, 20, 56 poc ............................................................................................................................... .............19, 20, 56 ppl ............................................................................................................................... ....................20, 62 prs ............................................................................................................................... ....................19, 21 r rch ............................................................................................................................... ...................19, 45 rcv ............................................................................................................................... ...................19, 45 rfh ............................................................................................................................... ....................19, 45 rfv ............................................................................................................................... ....................19, 45 rrp ............................................................................................................................... ...................16, 20 ru1 ............................................................................................................................... ..............20, 56, 63 ru2 ............................................................................................................................... ..............20, 56, 63 rue ............................................................................................................................... ...................20, 63 rwm ............................................................................................................................... 20, 27, 28, 61, 62 s s01 ............................................................................................................................... .....................20, 63 s02 ............................................................................................................................... .........20, 48, 56, 63 s03 ............................................................................................................................... .....................20, 56 s05 ............................................................................................................................... .....................20, 59 s09 ............................................................................................................................... ...........................20 s10 ............................................................................................................................... .....................20, 25 s11 ............................................................................................................................... .....................20, 59 s12 ............................................................................................................................... ...........................20 s13 ............................................................................................................................... .....................20, 25 s14 ............................................................................................................................... .....................20, 25 s19 ............................................................................................................................... ...........................20 sbh ............................................................................................................................... ....................19, 45 sbv ............................................................................................................................... ....................19, 45 sgh ............................................................................................................................... ...................19, 45 sgv ............................................................................................................................... ...................19, 45 srh ............................................................................................................................... ...................19, 45 srv ............................................................................................................................... ....................19, 45 sse ............................................................................................................................... ..........................20 sta ............................................................................................................................... ........19, 28, 29, 33 stl ............................................................................................................................... ...............20, 54, 56
82/83 stv2050a - index of i2c bus registers stv2050a code ............................................................................................................................... .....20 stx ............................................................................................................................... ........20, 27, 28, 29 t te2 ............................................................................................................................... ...........................20 te4 ............................................................................................................................... ...........................20 tol ............................................................................................................................... ....................19, 55 tvh ............................................................................................................................... ..............19, 42, 43 tvv ............................................................................................................................... ....................19, 43 v vae ............................................................................................................................... ....................19, 42 vbe ............................................................................................................................... ..........................19 vdc ............................................................................................................................... ...................20, 33 vfp ............................................................................................................................... ....................19, 52 vg1 ............................................................................................................................... ....................20, 39 vg2 ............................................................................................................................... ....................20, 39 vg3 ............................................................................................................................... ....................20, 59 vg4 ............................................................................................................................... ....................20, 59 vgd ............................................................................................................................... .......19, 34, 42, 52 vgp ............................................................................................................................... .............19, 34, 35 vhv ............................................................................................................................... ....................20, 37 vo1 ............................................................................................................................... ....................20, 39 vo2 ............................................................................................................................... ....................20, 39 vo3 ............................................................................................................................... ....................20, 59 vo4 ............................................................................................................................... ....................20, 59 vst ............................................................................................................................... ....................19, 25 vvb ............................................................................................................................... ..............19, 41, 42
83/83 stv2050a - index of i2c bus registers information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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